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MP1495S high efficiency 3a, 16v, 500k hz synchronous step - down converter MP1495S rev. 1.0 www.monolithicpower .com 1 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. description the MP1495S is a high - frequency , synchronous , rectified , step - down , switch - mode converter with built - in power mosfets. it offers a very compact solution to achieve a 3a continuous output current with excellent load and line regulation over a wi de input supply range. the MP1495S has synchronous mode operation for higher efficiency over the output current load range. current - mode operation provides fast transient response and eases loop stabilization. full protection features include over - current protection and thermal shut down. the MP1495S requires a minim al number of readily - available standard external components , and is available in a space - saving 8 - pin tsot23 package . features ? wide 4.5v - to - 16v operating input range ? 120 m / 5 0 m low r ds(on) i nternal power mosfets ? high - efficiency synchronous mode operation ? fixed 500 k hz switching frequency ? sync hronizes to a 3 00 k hz to 2mhz external clock ? aam power - save mode ? internal soft - start ? ocp protection and hiccup ? thermal shutdown ? output adjustable from 0.8 v ? available in an 8 - pin tsot - 23 package applications ? notebook systems and i/o power ? digital set - top boxes ? flat - panel television and monitors ? distributed power systems all mps parts are lead - free and adhere to the rohs directive. for mps green status, plea se visit mps website under quality assurance. mps and the future of analog ic technology are registered t rademarks of monolithic power systems, inc. typical application
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 2 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. ordering information part number* package top marking MP1495S g j tsot - 23 - 8 a gp f or tape & reel, add suffix C z ( e . g. MP1495S g j C z) ; package reference absolute maximum rat ings (1) v in ................................ ................ - 0.3v to 1 7 v v sw ................................ ................................ .... - 0.3v ( - 5v for <10ns) to 1 7 v (19v for <10ns ) v bs t ................................ ...................... v sw +6v all other pins ................................ - 0.3v to 6v (2) continuous power dissipation (t a = + 25 c) ( 3 ) ................................ .......................... 1. 25 w junction temperature .............................. 150 c lead temperature ................................ ... 260 c storage temperature ................. - 65 c to 150 c recommended operating conditions ( 4 ) supply voltage v in .......................... 4.5v to 16v output voltage v out .............. 0.8 v to v in x dmax operating junction temp . (t j ). - 40 c to +125 c thermal resistance ( 5 ) ja jc tsot - 23 - 8 ............................ 100 ..... 55 ... c/w notes: 1) exceeding these ratings may damage the device. 2) about the details of en pin s abs max rating, please refer to page 10 , enable/sync control sect i on. 3) the maximum allowable power dissipation is a function of the maximum jun ction temperature t j (max), t he junction - to - ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max) - t a )/ ja . exceeding the maximum a llowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 4) the device is not guaranteed to function outside of its operati ng conditions. 5) measured on jesd51 - 7, 4 - layer pcb.
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 3 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. electrical character istics v in = 12 v, t a = 25 c, unless otherwise noted. parameter symbol condition min typ max units supply current (shutdown) i in v en = 0v 1 a supply current (quiescent) i q v en = 2v, v fb = 1v , aam=0.5v 0.5 1 ma hs switch - on resistance hs rds - on v bst - sw =5v 120 m ls switch - on resistance ls rds - on v cc =5v 50 m switch leakage sw lkg v en = 0v, v sw = 12v 1 a current limit ( 6 ) i limit under 40% duty cycle 4. 5 6 a oscillator frequency f sw v fb =0.75v 410 50 0 580 k hz fold - back frequency f fb v fb =2 00mv 0.5 f sw maximum duty cycle d max v fb =700mv 90 9 5 % minimum on time (6) t o n_ min 60 n s sync frequency range f sync 0. 3 2 mhz feedback vol tage v fb t a =25 c 791 807 823 mv - 40 c MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 4 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. typical performance characteristics performance waveforms are tested on the evaluation board of the design example section . v in = 12 v, v out = 3.3 v, aam=0.5v , t a = 25 c, unless otherwise noted.
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 5 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. typical performance characteristics (continued) performance waveforms are tested on the evaluation board of the design example section . v in = 12 v, v out = 3.3 v, aam=0.5v , t a = 25 c, unless otherwise noted.
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 6 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. typical performance characteristics (continued) performance waveforms are tested on the evaluation board of the design example section . v in = 12 v, v out = 3.3 v, aam=0.5 v , t a = 25 c, unless otherwise noted.
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 7 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. typical performance characteristics (continued) performance waveforms are tested on the evaluation board of the design example section . v in = 12 v, v out = 3.3 v, aam=0.5v , t a = 25 c, unless otherwise noted.
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 8 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. pin funct ions package pin # name description 1 aam advanced asynchronous modulation. connect the tap of 2 resistor dividers to force the MP1495S into non - synchronous mode under light loads . drive aam pin high (v cc ) to force the MP1495S into ccm. 2 in supply volta ge. the MP1495S operates from a 4.5v to 16v input rail. requires c1 to decouple the input rail. connect using a wide pcb trace. 3 sw switch output. connect using a wide pcb trace. 4 gnd system ground. this pin is the reference ground of the regulated out put voltage , and pcb layout requires special care. for best results, connect to gnd with copper traces and vias. 5 bst bootstrap. requires a capacitor connected between sw and bs t pins to form a floating supply across the high - side switch driver. a 10 re sistor placed between sw and bst cap is strongly recommended to reduce sw spike voltage. 6 en/sync enable/synchronize. en high to enable the MP1495S . apply an external clock to the en pin to change the switching frequency. 7 vcc bias supply. decouple wi th 0.1 f - to - 0.22 f cap acitor . select a capacitor that does not exceed 0.22 f . vcc capacitor should be put closely to vcc pin and gnd pin . 8 fb feedback. connect to the tap of an external resistor divider from the output to gnd, to set the output voltage. the fr equency fold - back comparator lowers the oscillator frequency when the fb voltage is below 4 00mv to prevent current limit runaway during a short - circuit fault condition .
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 9 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. block diagram figure 1 : functional block diagram
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 10 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. operatio n the MP1495S is a high - frequency , synchronous , rectified , step - down , switch - mode converter with built - in power mosfets. it offers a very compact solution to achieve 3a continuous output current with excellent load and line regulation over a wide input su pply range . the MP1495S operates in a fixed - frequency, peak - current C control mode to regulate the output voltage. a n internal clock initiates a pwm cycle. the integrated high - side power mosfet turn s on and remains on until its current reaches the value set by the comp voltage. when the power switch is off, it remains off until the next clock cycle starts. if the current in the power mosfet does not reach the current value set by comp with in 9 5 % of one pwm period, the power mosfet will be forced to turn off . internal regulator the 5v internal regulator power most of the internal circuitries. this regulator takes the v in input and operates in the full v in range : when v in exceeds 5.0v, the output of the regulator is in full regulation ; when v in falls below 5.0v, the output decreases and requires a 0.1 f decoupling ceramic capacitor. error amplifier the error amplifier compares the fb pi n voltage against the internal 0.8 v reference (ref) and outputs a comp voltage this comp voltage control s the power mosfet curren t. the optimized internal compensation network minimizes the external component count and simplifies the control loop design. enable/sync control en/sync is a digital control pin that turns the regulator on and off : drive en high to turn on the regulator, drive it low to turn it off. an internal 1m ? resistor from en/sync to gnd allows en/sync to be floated to shut down the chip. the en pin is clamped internally using a 6. 5 v series zener diode , as shown in figure 2 . connect the en input pin through a pullup resistor to any v oltage connected to the v in pin the pullup resistor limits the en input current to less than 100a. for example, with 12v connected to v in , r pullup (12v C 6. 5 v ) 100a = 55 k? . connecting the en pin is directly to a voltage source without any pullup resistor requires limiting voltage amplitude to 6 v to prevent damage to the zener diode. figure 2 : 6.5v zener diode connect an external clock with a range of 3 00khz to 2mhz 2ms after output voltage is set to synchronize the inte rnal clock rising edge to the external clock rising edge. the pulse width of external clock signal should be less than 1.7 s. under - voltage lockout under - voltage lockout (uvlo) protect s the chip from operating at an insufficient supply voltage. the MP1495S uvlo comparator monitors the output voltage of the internal regulator, vcc. the uvlo rising threshold is about 3. 8 v while its falling threshold is 3. 15 v . internal soft - start the soft - start prevent s the converter output voltage from overshooting during sta rtup. when the chip starts, the internal circuitry generates a soft - start voltage (ss) that ramps up from 0v to 1.2v. when ss is lower than ref, ss overrides ref so the error amplifier uses ss as the reference. when ss exceeds ref, the error amplifier uses ref as the reference . the ss time is internally set to 1.5 ms. over - current protection and hiccup the MP1495S has cycle - by - cycle over current limit for when the inductor current peak value exceeds the set current limit threshold. if the output voltage star ts to drop until fb is below the under - voltage (uv) threshold typically 5 0 % below the reference the MP1495S enters hiccup mode to periodically restart the part.
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 11 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. this protection mode is especially useful when the output is dead - short ed to ground. the averag e short - circuit current is greatly reduced to alleviate the thermal issue and to protect the regulator. the MP1495S exits the hiccup mode once the over - current condition is removed. thermal shutdown thermal shutdown prevent s the chip from operating at exce edingly high temperatures. when the silicon die temperature exceeds 150c, it shuts down the whole chip. when the temperature drops below its lower threshold ( typically 130c ) the chip is enabled again. floating driver and bootstrap charging an external bo otstrap capacitor powers the floating power mosfet driver. this floating driver has its own uvlo protection , with a rising threshold of 2.2v and hysteresis of 150mv. the bootstrap capacitor voltage is regulated internally by v in through d1, m 1 , c4, l1 and c2 ( figure 3 ). if (v in - v sw ) exceeds 5v, u 1 regulate s m 1 to maintain a 5v bst voltage across c4. a 10 resistor placed between sw and bst cap is strongly recommended to reduce sw spike voltage. figure 3 : internal bootstrap charging circuit startup and shutdown if both v in and en exceed their appropriate thresholds, the chip star ts : the reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. the regulator provides stable supply for the remaining circuitries. three events can shut down the chip: en low, v in low , an d thermal shutdown. in the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. the comp voltage and the internal supply rail are then pulled down. the floating driver is not subject to this shutdown command.
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 12 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. application information setting the output voltage the external resistor divider set s the output voltage . the feedback resistor r1 also sets the feedback loop bandwidth with the internal compensation capacitor (see typical application on page 1). choose r1 around 40 k , then r2 is: use the t - type network when v out is low, as show n in figure 4 . figure 4 : t - type network table 1 lists the recommended t - ty pe resistor value for common output voltages. table 1 : resistor selection for common output voltages v out (v) r1 (k?) (k?) (k?) 1.0 20.5 8 4.5 82 15 1.8 1.2 30.1 6 1.9 82 15 1.8 1.8 40.2 32.4 56 15 3.3 2.5 40. 2 1 9.1 33 15 3.3 3.3 40.2 13 33 15 4.7 5 40.2 7.68 33 15 4.7 selecting the inductor for most applications, use a 1h - to - 22 h inductor with a dc current rating that is at least 25% percent higher than the maximum load current. select an inductor with a d c resistance less than 15m? for highest efficiency . for most designs, the inductance value can be derived from the following equation. where i l is the inductor ripple current. choose an inductor ripple current to be approximately 30% o f the ma ximum load current . the maximum inductor peak current is: use a larger inductor for light - load conditions ( below 100ma ) for improved efficiency. setting the aam voltage the aam voltage set s the transition point from aam to ccm. sele ct a voltage that balances efficiency, stability, ripple, and transient : a relatively low aam voltage improves stability and ripple , but degrades transient and efficiency during aam mode ; a relatively high aam voltage improves the transient and efficiency during aam , but degrades stability and ripple. aam voltage is set from the tap of a resistor divider from the v cc (5v) pin , as shown in figure 5 . figure 5 : aam network generally, choose r 5 to be around 10 0 k? , then r 6 is: figure 6 : aam selection for common output voltages (v in =4.5v to 16v) out r1 r2 v 1 0.807v ? ? out in out 1 in l osc v (v v ) l v i f ?? ? ? ? ? 2 i i i l load ) max ( l ? ? ? aam cc aam v r6 r5 vv ?? ?
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 13 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. selecting the input capacitor the input current to the step - down converter is discontinuous and therefore requires a cap acitor to supply the ac current to the step - down converter while maintaining the dc input voltage. use low - esr capacitors for the best performance. for best results, use ceramic capacitors with x5r or x7r dielectrics because of their low esr and small temp erature coefficients. use a 22f capacitor for most applications. c1 requires an adequate ripple current rating since it absorbs the input switching current. estimate the rms current in the input capacitor with : the wors t case condi tion occurs at v in = 2v out , where: for simplification, choose an input capacitor whose rms current rating greater than half of the maximum load current. the input capacitor can be electrolytic, tantalum or ceramic. when using electr olytic or tantalum capacitors, place a small, high - quality ceramic capacitor (e.g. 0.1f ) as close to the ic as possible. when using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at the input. the input voltage ripple caused by capacitance can be estimated by: selecting the output capacitor the output capacitor (c2) maintain s the dc output voltage. use ceramic , tantalum, or low - esr electrolytic capacitors. for best results, use low - esr capacitors to keep the output voltage ripple lo w. the output voltage ripple can be estimated by: where l 1 is the inductor value and r esr is the equivalent series resistance (esr) value of the output capacitor. for ceramic capacitors, the capacitance dominates the impedance at t he switching frequency , and thus causes the majority of the output voltage ripple. for simplification, the output voltage ripple can be estimated by: for tantalum or electrolytic capacitors, the esr dominates the impedance at the s witching frequency. for simplification, the output ripple can be approximated to: the characteristics of the output capacitor also affect the stability of the regulation system. the MP1495S can be optimized for a wide range of capac itance and esr values. ? ? ? ? ? ? ? ? ? ? ? ? in out in out load 1 c v v 1 v v i i 2 i i load 1 c ? load out out in in s in i v v v1 f c1 v v ?? ? ? ? ? ? ?? ? ?? out out out esr s 1 in s vv 1 v 1 r f l v 8 f c2 ?? ?? ? ? ? ? ? ? ?? ?? ? ? ? ?? ?? out out out 2 in s1 vv v 1 v 8 f l c2 ?? ? ? ? ?? ? ? ? ?? out out out esr in s1 vv v 1 r f l v ?? ? ? ? ? ?? ? ??
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 14 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. pc board layout ( 8 ) pcb layout is very important to achieve stable operation especially for vcc capacitor and input capacitor placement. for best results, follow these guidelines: 1 ) use large ground plane directly connect to gnd pin. add vias near the gnd pin if bottom layer is ground plane. 2 ) place the vcc capacitor to vcc pin and gnd pin as close as possible. make the trace length of vcc pin - vcc capacitor anode - vcc capacitor cathode - chip gnd pin as short as possible. 3 ) place the ceramic input capacitor close to in and gnd pins. keep the connection of input capacitor and in pin as short and wide as possible. 4) route sw, bst away from sensitive analog areas such as fb. its not recommended to route sw, bst trace under chips bo ttom side. 5) place the t - type feedback resistor r 7 close to chip to ensure the trace which connects to fb pin as short as possible notes: 8) the recommended layout is based on the figure 8 typical application circuit on the next page. design example below i s a design example following the application guidelines for the specifications: table 2: design example v in 12 v v out 3.3 v io 3a the detailed application schematic is shown in fig ure 8 . the typical performance and circuit waveforms have been shown in the typical perfor mance characteristics section. for more device applications, please refer to the related evaluation board data sheets. g n d sw bst g n d v o u t en / s y n c v c c en / s y n c v c c 8 7 6 5 c 2 c 1 c 1 a r 2 r 3 c 4 1 2 3 4 v in g n d v o u t sw g n d c 3 r 1 r 7 c 2 a r 5 r 6 c 6 c 5 r 4 l 1
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 15 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. typical application circuits figure 7 : 12v in , 5 v/3a output fig ure 8 : 12v in , 3.3 v/3a output figure 9 : 12v in , 2.5 v/3a output m p 1 4 9 5 s c 1 0 . 1 f c 1 a 2 2 f c 6 0 . 1 f r 5 1 0 0 k r 6 1 2 . 7 k r 4 1 0 0 k r 3 1 0 c 4 0 . 1 f l 1 4 . 7 h c 2 a 2 2 f c 2 2 2 f c 5 1 n f r 7 3 3 k r 1 4 0 . 2 k r 2 7 . 6 8 k c 3 1 5 p f 5 v / 3 a u 1 v i n v c c a a m e n v o u t g n d g n d m p 1 4 9 5 s c 1 0 . 1 f c 1 a 2 2 f c 6 0 . 1 f r 5 1 0 0 k r 6 1 1 . 3 k r 4 1 0 0 k r 3 1 0 c 4 0 . 1 f l 1 4 . 7 h c 2 a 2 2 f c 2 2 2 f c 5 1 n f r 7 3 3 k r 1 4 0 . 2 k r 2 1 3 k c 3 1 5 p f 3 . 3 v / 3 a u 1 v i n v c c a a m e n v o u t g n d g n d m p 1 4 9 5 s c 1 0 . 1 f c 1 a 2 2 f c 6 0 . 1 f r 5 1 0 0 k r 6 1 0 k r 4 1 0 0 k r 3 1 0 c 4 0 . 1 f l 1 3 . 3 h c 2 a 2 2 f c 2 2 2 f c 5 1 n f r 7 3 3 k r 1 4 0 . 2 k r 2 1 9 . 1 k c 3 1 5 p f 2 . 5 v / 3 a u 1 v i n v c c a a m e n v o u t g n d g n d
MP1495S C synchronous st ep - down converter MP1495S rev. 1.0 www.monolithicpower .com 16 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. figure 10 : 12v in , 1.8 v/3a output figure 11 : 12v in , 1.2 v/3a output figure 12 : 12v in , 1 v/3a output m p 1 4 9 5 s c 1 0 . 1 f c 1 a 2 2 f c 6 0 . 1 f r 5 1 0 0 k r 6 8 . 8 7 k r 4 1 0 0 k r 3 1 0 c 4 0 . 1 f l 1 3 . 3 h c 2 a 2 2 f c 2 2 2 f c 5 1 n f r 7 5 6 k r 1 4 0 . 2 k r 2 3 2 . 4 k c 3 1 5 p f 1 . 8 v / 3 a u 1 v i n v c c a a m e n v o u t g n d g n d m p 1 4 9 5 s c 1 0 . 1 f c 1 a 2 2 f c 6 0 . 1 f r 5 1 0 0 k r 6 9 . 3 1 k r 4 1 0 0 k r 3 1 0 c 4 0 . 1 f l 1 1 . 8 h c 2 a 2 2 f c 2 2 2 f c 5 1 n f r 7 8 2 k r 1 3 0 . 1 k r 2 6 1 . 9 k c 3 1 5 p f 1 . 2 v / 3 a u 1 v i n v c c a a m e n v o u t g n d g n d m p 1 4 9 5 s c 1 0 . 1 f c 1 a 2 2 f c 6 0 . 1 f r 5 1 0 0 k r 6 7 . 8 7 k r 4 1 0 0 k r 3 1 0 c 4 0 . 1 f l 1 1 . 8 h c 2 a 2 2 f c 2 2 2 f c 5 1 n f r 7 8 2 k r 1 2 0 . 5 k r 2 8 4 . 5 k c 3 1 5 p f 1 v / 3 a u 1 v i n v c c a a m e n v o u t g n d g n d
MP1495S C synchronous step - down converter notice: the information in this document is subject to change without notice. users should warrant and guarantee that third party intellectual property rights are not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP1495S rev. 1.0 www.monolithicpower.com 17 12/13/2013 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2013 mps . all rights reserved. package information tsot23 - 8 front view note : 1 ) all dimensions are in millimeters . 2 ) package length does not include mold flash , protrusion or gate burr . 3 ) package width does not include interlead flash or protrusion . 4 ) lead coplanarity ( bottom of leads after forming ) shall be 0 . 10 millimeters max . 5 ) jedec reference is mo - 193 , variation ba . 6 ) drawing is not to scale . 7 ) pin 1 is lower left pin when reading top mark from left to right , ( see example top mark ) top view recommended land pattern seating plane side view detail '' a '' see detail '' a '' iaaaa pin 1 id see note 7 example top mark

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